Non-volatile memory cells having a floating gate for the storage of charges thereon are well known in the art. Referring to FIG. 1 there is shown a cross-sectional view of a non-volatile memory cell 10 of the prior art. The memory cell 10 comprises a single crystalline substrate 12, of a first conductivity type, such as P type. At or near a surface of the substrate 12 is a first region 14 of a second conductivity type, such as N type. Spaced apart from the first region 14 is a second region 16 also of the second conductivity type. Between the first region 14 and the second region 16 is a channel region 18. A word line 20, made of polysilicon is positioned over a first portion of the channel region 18. The word line 20 is spaced apart from the channel region 18 by an insulating layer 22, such as silicon (di)oxide. Immediately adjacent to and spaced apart from the word line 20 is a floating gate 24, which is also made of polysilicon, and is positioned over another portion of the channel region 18. The floating gate 24 is separated from the channel region 18 by another insulating layer 30, typically also of silicon (di)oxide. A coupling gate 26, also made of polysilicon is positioned over the floating gate 24 and is insulated therefrom by another insulating layer 32. On another side of the floating gate 24, and spaced apart therefrom, is an erase gate 28, also made of polysilicon. The erase gate 28 is positioned over the second region 16 and is insulated therefrom. The erase gate 28 is adjacent to and spaced apart from the coupling gate 26. The erase gate 28 can have a slight overhang over the floating gate 24. In the operation of the memory cell 10, charge stored on the floating gate 24 controls the flow of current between the first region 14 and the second region 16. Where the floating gate 24 is negatively charged thereon, the memory cell is programmed. Where the floating gate 24 is positively charged thereon, the memory cell is erased. The memory cell 10 is fully disclosed in U.S. Pat. No. 7,868,375 whose disclosure is incorporated herein in its entirety by reference.
The memory cell 10 operates as follows. During the programming operation, when electrons are injected to the floating gate 24 through hot-electron injection with the portion of the channel 18 under the floating gate 24 in inversion, a first positive voltage in the shape of a pulse is applied to the word line 20 causing the portion of the channel region 18 under the word line 20 to be conductive. A second positive voltage, also in the shape of a pulse, is applied to the coupling gate 26, to utilize high coupling ratio between coupling gate 26 and floating gate 24 to maximize the voltage coupling to the floating gate 24. A third positive voltage, also in the shape of a pulse, is applied to the erase gate 28, to utilize coupling ratio between erase gate 28 and floating gate 24 to maximize the voltage coupling to the floating gate 24. A voltage differential, also in the shape of a pulse, is applied between the first region 14 and the second region 16, to provide generation of hot electrons in the channel 18. All of the first positive voltage, second positive voltage, third positive voltage and the voltage differential are applied substantially at the same time, and terminate substantially at the same time. During programming operation the potential on the floating gate 24 monotonically reduces from a highest value at the beginning of programming operation to a lowest value at the end of programming operation.
During the erase operation, when electrons are removed from the floating gate 24, a high positive voltage is applied to the erase gate 28. A negative voltage or ground voltage can be applied to the coupling gate 26 and/or the word line 20. Electrons are transferred from the floating gate 24 to the erase gate 28 by Fowler-Nordheim tunneling through the insulating layer between the floating gate 24 and the erase gate 28. In particular, the floating gate 24 may be formed with a sharp tip facing the erase gate 28, thereby facilitating said tunneling of electrons.
During the read operation, a first positive voltage is applied to the word line 20 to turn on the portion of the channel region 18 beneath the word line 20. A second positive voltage is applied to the coupling gate 26. A voltage differential is applied to the first region 14 and the second region 16. If the floating gate 24 were programmed, i.e. the floating gate 24 stores electrons, then the second positive voltage applied to the coupling gate 26 is not able to overcome the negative electrons stored on the floating gate 24 and the portion of the channel region 18 beneath the floating gate 24 remains non-conductive. Thus, no current or a negligibly small amount of current would flow between the first region 14 and the second region 16. However, if the floating gate 24 were not programmed, i.e. the floating gate 24 remains neutral or positively charged, then the second positive voltage applied to the coupling gate 26 is able to cause the portion of the channel region 18 beneath the floating gate 24 to be conductive. Thus, a current would flow between the first region 14 and the second region 16.
As is well known, memory cells 10 are typically formed in an array, having a plurality of rows and columns of memory cells 10, on a semiconductor wafer. One of the uses for an array of floating gate non-volatile memory cells is as a smart card. However, in such application, the array of non-volatile memory cells must have high program/erase endurance. In the prior art, during programming a high voltage has been applied to the coupling gate 26 and erase gate 28 in order to induce sufficient potential on the floating gate 24 to cause hot electrons to be injected from the channel region 18 to the floating gate 24. However, the maximum potential induced on the floating gate 24 at the beginning of programming operation can cause relatively fast degradation of the insulating layer 30 between the floating gate 24 and the channel region 18 as well as the interface between the channel region 18 and the insulating layer 30. The degradation of these areas is a major factor which affects program/erase endurance of a memory cell.
The prior art also discloses applying a ramped voltage to the coupling gate 26 of a memory cell having a word line gate 20 and a coupling gate 26 (but without an erase gate) during programming to increase the endurance of the memory cell. See “Method For Endurance Optimization of The HIMOS Flash Memory Cell” by Yao et al, IEEE 43rd Annual International Reliability Physics Symposium, San Jose, 2005, pp. 662-663.
The memory cell 10 does not require a high voltage to be applied to the second region 16 to cause programming, which enables high program/erase endurance. Nevertheless, the prior art method of programming has not been optimized for high program/erase endurance. Hence, one object of the present invention is to optimize the parameters for programming the memory cell of the type shown in FIG. 1 so that endurance is further increased.